Not applicable.
This invention relates generally to electrical connections between layers of multi-layer printed circuit boards and more particularly to a class of layer-to-layer interconnections referred to as via circuits or more simply vias.
As is known in the art, there exists a class of electrical connection structures, referred to as plated through holes (PTHs) or via circuits or more simply vias, which provide layer-to-layer interconnections in multi-layer printed circuit boards (PCBs).
A conventional via in a multi-layer PCB is typically provided by drilling or otherwise forming a hole through the PCB. The through hole passes through all conductive layer traces in the PCB which are intended to be connected. The hole is then plated to form an electrical connection among the conductive traces. In this manner, electrical connections between layers of multi-layer PCBs can be provided. This process can be used to provide a signal path through which a single signal propagates between layers of a PCB. Connections to conductive traces or signal paths in each of the PCB layers can be made. This via connection technique conserves space on the PCB and thus allows PCBs to be more densely populated.
The via has been the mainstay of layer-to-layer interconnection since the inception of double-sided and multi-layer boards. Originally vias served dual purposes, providing layer-to-layer interconnect and through-hole component mount. The growth of surface mount component technology (with the exception of backplane connectors and other large devices), however, has reduced the need to utilize vias for through-hole component mount and has resulted in the via primarily providing layer-to-layer interconnection.
There has, however, been a trend to provide PCBs having increasingly higher circuit density and higher circuit speed. To help meet the demand for increased circuit density, it has been proposed to provide more than one independent signal path or connection in a single via. To provide multiple connections in the same via of a PCB, the via is formed as described above. Discrete connections are then formed among the conductive traces of the PCB by establishing grooves in the plating of the via to electrically isolate segments of the PCB. This technique permits two or more independent connections to be made in the same via of a multi-layer PCB. This technique further conserves space on the PCB and thus allows PCBs to be even more densely populated.
Despite the advances made in increasing circuit density on PCBs, the high performance requirements of modern integrated circuit (IC) devices impose requirements for increasingly higher density of interconnections on PCBs so that the PCBs can accept the large number of input and output signal lines from IC devices which are packaged into increasingly smaller volumes. All of these design and performance considerations add to the difficulties in attempting to lower PCB production costs which are increasing due to the use of complicated multiple-layer substrates.
Furthermore, modem IC devices operates at increasingly higher frequencies. As clock frequencies of circuits used on PCBs exceed 100 MHz, the electrical characteristics of PCB traces resemble high-speed signal transmission lines rather than D.C. electrical circuits. The higher clock frequencies and resultant shorter signal rise times expose PCB performance limitations which are manifested by signal integrity phenomena such as ringing, reflections, ground bounce, and crosstalk.
State of the art computer motherboards operate at frequencies of 100 MHz and above, while telecommunications and high performance systems use device to board frequencies an order of magnitude higher. High performance systems having chip-to-board clock speeds in the GHz range are expected. To support these current and future performance demands, improvement gains in PCB technology are required.
To address the above density and speed concerns xe2x80x9cbuildup technologiesxe2x80x9d such as photo-via redistribution, and sheet buildup, have been developed. These techniques have increased PCB performance significantly. These techniques, however, rely on thinner layers and use chemical etching (photo-defined vias), laser ablation, or plasma etching technologies to drill holes and connect PC board layers. Thus, such techniques are not appropriate for use in PCBs which include a relatively large number of layers between signal paths which must be connected.
So-called micro-vias have also been proposed. Both the signal and density performance of micro-vias are very good in comparison to drilled vias. There are still discontinuities in the signal path, because the ground plane is disrupted. However, because the scale is so small, this problem is minimal, especially when only going through one layer (which does not break the continuous ground path). Micro-vias are particularly useful in applications in which the number of PCB layers is relatively small or where density is extreme, such as in micro ball grid array (xcexcBGA) escapement. As an added benefit, micro-vias can be placed directly in a surface mount pad.
Because micro-vias must be manufactured from the outer surface (often out of non-woven aramid reinforced layers or unreinforced dielectric), the micro-vias can only be on the outer traces unless subsequent layers are built on top of the constructed panel. Each layer adds significant processing cost. Via depth is limited greatly because the plating chemistry cannot flow through small blind holes in the same manner as through-hole vias. Similar limitations exist for laser ablated and co-deposition vias. Thus, micro-vias are also not particularly useful in PCBs which include a relatively large number of layers between signal paths which must be connected.
Furthermore, none of the above techniques address the problem of maintaining signal strength and quality (i.e. shape of signal, lack of noise from either internal reflections or cross talk from other lines) collectively referred to herein as signal integrity as device operating frequencies increase and/or clock rise times decrease. Moreover, owing to the addition of noise as well as reflections due to impedance mismatches, signal quality suffers when the impedance of the layer-to-layer interconnection transmission structure changes, resulting in parasitic wave reflections and in some cases resonation. This results in a signal path having a relatively high insertion loss characteristic. A secondary related effect is crosstalk, which relates to the electromagnetic interference (EMI) between circuit structures. Thus, one problem with the prior art approaches, is that they merely attempt to increase density on a printed circuit board and they fail to provide any mechanisms for maintaining signal integrity and signal quality.
It would, therefore, be desirable to provide an interconnection structure which provides a layer-to-layer signal path which is relatively low loss, which does not degrade signal performance, which maintains signal integrity and which allows increased density of connections. It would also be desirable to provide an interconnection structure which is easily adapted to work with existing PCB manufacturing techniques, components and the like.
It would further be desirable to provide an interconnection structure which reduces the number and magnitude of impedance discontinuities due to transmission structure changes and which reduces the amount of crosstalk between circuit structures.
It has, in accordance with the present invention, been recognized that although signal lines within a single printed circuit board (PCB) layer are provided having predetermined impedance characteristics (i.e. the impedance of the signal line is controlled), such impedance control is not available for conventional plated-through holes (PTHs) which are used to provide signal paths between different layers of the PCB. This lack of control of the impedance characteristics of the via results in relatively large impedance mismatches between the via and other circuits/circuitry. Thus, the vias have relatively high insertion loss characteristics due primarily to impedance mismatch.
Because the via are lossy, there has been a desire and need to minimize number of vias on PCBs. In an effort to minimize the number of vias, circuit traces are ideally limited to a single plane (i.e. a single layer) in the PCB. Limiting the circuit traces to a single plane, however also limits the number of possible circuit layout which are available to a circuit board designer.
In accordance with the present invention, an interconnection structure for providing a signal path between a first layer and a second different layer of a multi-layer structure includes a via having a plurality of electrically isolated segments with at least one of the electrically isolated segments coupled to a signal path and at least one of the electrically isolated segments coupled to ground. With this particular arrangement, a multi-connection via (MCV) which does not degrade signal performance, signal integrity or signal quality of relatively high frequency signals is provided. By coupling a first segment of the via to a signal path and having a second segment of the via in proximity to the first segment coupled to ground, a defined electric field pattern is established in the via when signals having a relatively high frequency propagate through the via. By providing a structure through which a signal can propagate with a defined electric field pattern, the MCV provides a signal path having a relatively low insertion loss characteristic to relatively high frequency signals propagating therethrough. The impedance characteristic of the via can be selected by appropriately selecting a variety of via characteristics including but not limited to the hole diameter of the via and the relative widths of the signal and ground segments.
This allows manufacture of printed circuit boards (PCBs) which include vias having a relatively low insertion loss characteristic and a relatively low return loss characteristic. The vias provide signal paths having a relatively low insertion loss characteristic because the vias can be designed and manufactured having defined impedance characteristics. The via can thus be designed to better match (in an impedance matching sense) the IC devices or circuits or signal paths coupled thereto. Because the via of the present invention provides a relatively low loss, reliable signal path between layers of a multi-layer printed circuit board, it is not necessary to restrict the PCB circuit layouts to a single layer or plane. Consequently reducing the number of required layers in a PCB.
Furthermore the MCV of the present invention can be provided having multiple signal segments and/or multiple ground segments to thus allow inclusion of more signal traces in a single via. This allows the manufacture of PCBs having relatively high circuit density. The MCV of the present invention allows impedance control of signal paths between layers of a multi-layer PCB and thereby allows use of a connector which integrates tightly with the PCB. This type of impedance control is not possible with conventional via technologies, including advanced structures such as micro vias. Thus the MCV of the present invention. This ability fundamentally changes routing rules for high speed signal traces, allowing for layer changes without concern of signal degradation. Furthermore, signal performance of the co-cylindrical wave-guide structure is completely independent of diameter. Moreover, MCVs having multiple signal and ground segments which provide improved electrical performance allow further increases in connection density.
The MCV may be considered as a xe2x80x9cshielded viaxe2x80x9d which offers improved performance to connectors and devices without requiring design changes of the PCB, connectors or devices. That is, the MCV of the present invention is compatible with conventional PCB manufacturing processes including PCB via manufacturing processes.
To construct multi-connection vias in PCBs for signal experiments, a broach process can be used to segment plated-through holes to provide isolated segments. Alternatively, MCVs can be provided using an electrical discharge machining (EDM) process. In utilizing the EDM process it should be noted that to properly utilize an EDM process to manufacture the multi-connection vias, it is necessary to provide a signal path from each of the individual segments of the via to ground during the EDM process.
In accordance with a still further aspect of the present invention a method of routing signal traces in multi-layer printed circuit board using a multi-connection via (MCV) includes the steps of providing a multi-connection via having at least a pair of signal segments and at least one ground segment, connecting a first signal trace to a first one of the pair of signal segments, connecting a second signal trace to a second different one of the pair of signal segments and connecting the ground segment to a groundplane layer of the multi-layer printed circuit board. With this arrangement, a technique for reducing the number of vias provided in a multi-layer printed circuit board to route signal traces between different layers of the multi-layer printed circuit board is provided. This routing technique utilizing MCVs finds particular applicability when routing high speed signal traces in PCBs and maintaining signal integrity is an important concern.
In accordance with a still further aspect of the present invention, a multi-connection via launch includes a connector having a signal contact and ground contact disposed in an MCV. The MCV includes a ground via segment coupled to a ground plane and the ground contact of the connector and a signal via segment coupled to a signal trace and the signal contact of the connector. Since the impedance characteristics of the MCV can be controlled, the MCV can act as an impedance matching structure between the connector and the signal trace on the PCB. This arrangement solves the problem of device and connector launch to the PCB which represents a major discontinuity in a signal path. The performance benefits provided by the MCV""s impedance-controlled structure throughout the transition thus carry over to PCB connector and device launches.